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Assembly Language

register set

summary

This spider web page examines the use of registers in assembly linguistic communication. Specific examples of registers from various processors are used to illustrate the general nature of assembly linguistic communication.

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tabular array of contents for assembly language section
register set up

accumulators
information registers
address registers
general purpose registers
constant registers
floating point registers
index registers
base of operations registers
command registers
program counter (location counter)
processor flags

result flags
command flags

stack pointer
subroutine return pointer

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register set

Registers are fast memory, almost always continued to circuitry that allows various arithmetic, logical, command, and other manipulations, equally well as possibly setting internal flags.

About early on computers had just one data register that could be used for arithmetic and logic instructions. Often there would be additional special purpose registers set aside either for temporary fast internal storage or assigned to logic circuits to implement certain instructions. Some early computers had one or two address registers that pointed to a memory location for retentiveness accesses (a pair of address registers typically would act as source and destination pointers for memory operations). Computers soon had multiple information registers, address registers, and sometimes other special purpose registers. Some computers accept general purpose registers that tin can exist used for both data and address operations. Every digital computer using a von Neumann architecture has a annals (called the program counter) that points to the side by side executable educational activity. Many computers accept additional control registers for implementing diverse command capabilities. Often some or all of the internal flags are combined into a flag or status register.

accumulators

Accumulators are registers that tin be used for arithmetic, logical, shift, rotate, or other similar operations. The outset computers typically only had i accumulator. Many times in that location were related special purpose registers that independent the source data for an accumulator. Accumulators were replaced with data registers and general purpose registers. Accumulators reappeared in the first microprocessors.

Intel 8086/80286: one word (16 flake) accumulator; named AX (high order byte of the AX register is named AH and low order byte of the AX annals is named AL)
Intel 80386: 1 doubleword (32 chip) accumulator; named EAX (depression order word uses the same names as the accumulator on the Intel 8086 and 80286 [AX] and low order and high society bytes of the low society words of iv of the registers utilise the same names as the accumulator on the Intel 8086 and 80286 [AH and AL])
MIX: one accumulator; named A-register; five bytes plus sign

data registers

Data registers are used for temporary scratch storage of information, besides as for data manipulations (arithmetic, logic, etc.). In some processors, all data registers act in the same manner, while in other processors different operations are performed are specific registers.

MIX: ane extension register; named X-register; five bytes plus sign; tin can be concatenated on the right hand side of the A-register (accumulator)
Motorola 680x0, 68300: 8 longword (32 bit) data registers; named D0, D1, D2, D3, D4, D5, D6, and D7

address registers

Address registers store the addresses of specific memory locations. Often many integer and logic operations can be performed on address registers directly (to allow for computation of addresses).

Sometimes the contents of address register(s) are combined with other special purpose registers to compute the bodily concrete address. This allows for the hardware implementation of dynamic memory pages, virtual memory, and protected retentiveness.

The number of bits of an address register (perchance combined with data from other registers) limits the maximum amount of addressable retention. A 16-bit address register can address 64K of physical memory. A 24-fleck address register can address address sixteen MB of physical retention. A 32-bit accost register tin address 4 GB of physical retentiveness. A 64-bit address register can address 1.8446744 10 10¹⁹ of physical memory. Addresses are ever unsigned binary numbers. See number of bits.

MIX: i jump registers; named J-annals; 2 bytes and sign is always positive
Motorola 680x0, 68300: 8 longword (32 flake) address registers; named A0, A1, A2, A3, A4, A5, A6, and A7 (likewise called the stack arrow)

general purpose registers

General purpose registers can exist used as either data or accost registers.

December VAX: xvi word (32 bit) general purpose registers; named R0 through R15
IBM 360/370: 16 full discussion (32 bit) general purpose registers; named 0, 1, 2, 3, four, five, half-dozen, 7, eight, 9, A (or x), B (or 11), C (or 12), D (or 13), E (or fourteen), and F (or 15)
Intel 8086/80286: eight word (sixteen bit) general purpose registers; named AX, BX, CX, DX, BP, SP, SI, and DI (loftier order bytes of the AX, BX, CX, and DX registers take the names AH, BH, CH, and DH and low club bytes of the AX, BX, CX, and DX registers take the names AL, BL, CL, and DL)
Intel 80386: viii doubleword (32 flake) general purpose registers; named EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI (low order words use the same names every bit the general purpose registers on the Intel 8086 and 80286 and low order and high social club bytes of the depression lodge words of four of the registers use the same names as the general purpose registers on the Intel 8086 and 80286)
Motorola 88100: 32 word (32 flake) full general purpose registers; named r0 through r31

constant registers

Constant registers are special read-only registers that shop a constant. Attempts to write to a constant register are illegal or ignored. In some RISC processors, constant registers are used to store usually used values (such as goose egg, one, or negative 1) — for example, a abiding annals containing zero can be used in register to register data moves, providing the equivalent of a articulate education without adding ane to the pedagogy set. Constant registers are besides often used in floating point units to provide such value as pi or e with additional hidden $.25 for greater accuracy in computations.

Motorola 88100: r0 (general purpose register 0) contains the constant 32 bit integer nix

floating bespeak registers

Floating indicate registers are special registers set up aside for floating betoken math.

alphabetize registers

Index registers are used to provide more flexibility in addressing modes, allowing the developer to create a memory address past combining the contents of an address register with the contents of an index register (with displacements, increments, decrements, and other options). In some processors, there are specific index registers (or but one alphabetize register) that tin only be used only for that purpose. In some processors, any data annals, address annals, or general register (or some combination of the three) tin can exist used as an index register.

IBM 360/370: any of the xvi general purpose registers may be used every bit an index register
Intel 80x86: 7 of the viii general purpose registers may be used as an index register (the ESP is the exception)
MIX: v index registers; named I-registers I1, I2, I3, I4, and I5; five bytes plus sign
Motorola 680x0, 68300: whatsoever of the 8 data registers or the 8 address registers may be used as an index register

base registers

Base of operations registers or segment registers are used to segment memory. Effective addresses are computed past adding the contents of the base of operations or segment register to the rest of the effective address computation. In some processors, any register tin serve as a base of operations annals. In some processors, in that location are specific base or segment registers (i or more than) that tin can but exist used for that purpose. In some processors with multiple base or segment registers, each base or segment register is used for different kinds of memory accesses (such as a segment register for information accesses and a dissimilar segment register for program accesses).

IBM 360/370: any of the 16 general purpose registers may be used every bit a base of operations register
Intel 80x86: 6 defended segment registers: CS (lawmaking segment), SS (stack segment), DS (data segment), ES (extra segment, a second data segment register), FS (third data segment register), and GS (fourth data segment register)
Motorola 680x0, 68300: any of the 8 address registers may be used as a base register

control registers

Control registers control some aspect of processor functioning. The well-nigh universal control register is the programme counter.

program counter

Near every digital calculator ever made uses a programme counter. The program counter points to the memory location that stores the next executable instruction. Branching is implemented by making changes to the program counter. Some processor designs permit software to directly alter the programme counter, but normally software only indirectly changes the program counter (for example, a Leap didactics volition insert the operand into the programme counter). An assembler has a location counter, which is an internal arrow to the address (first byte) of the side by side location in storage (for instructions, data areas, constants, etc.) while the source code is being converted into object code.

The VAX uses the 16th of sixteen general purpose registers as the program counter (PC). Almost the entire instruction ready can straight dispense the program counter, assuasive a very rich prepare of possible kinds of branching.

The program counter in Organization/360 and 370 machines is contained in bits 40-63 of the plan status discussion (PSW), which is directly attainable past some instructions.

IBM 360/370: plan counter is bits 40-63 of the plan status word (PSW)
Intel 8086/80286: xvi-bit instruction arrow (IP)
Intel 80386: 32-chip education arrow (EIP)
Motorola 680x0, 68300: 32-fleck program counter (PC)

processor flags

Processor flags store information about specific processor functions. The processor flags are usually kept in a flag register or a general status register. This tin can include upshot flags that record the results of certain kinds of testing, information about data that is moved, certain kinds of information about the results of compations or transformations, and data about some processor states. Closely related and often stored in the aforementioned processor word or status annals (although often in a privileged portion) are control flags that command processor actions or processor states or the deportment of certain instructions.

IBM 360/370: program status discussion (PSW)
Intel 8086/80286: 16-bit flag annals (FLAGS); system flags, command flag, and condition flags)
Intel 80386: 32-scrap flag annals (EFLAGS); organization flags, control flag, and status flags)
MIX: an overflow toggle and a comparison indicator
Motorola 680x0, 68300: 16-fleck status register (SR); loftier byte is system byte and requires privileged admission, depression byte is user byte or condition code register (CCR)

A few typical event flags (with processors that include them):

auxilary carry Set if a bear out of the nigh significant bit of a BCD operand occurs (binary coded decimal addition). Likewise commonly ready if a borrow occurs in a BCD decrease. Used in Intel 80x86 [AF].
acquit Set if a acquit out of the most significant chip of an operand occurs (addition). As well commonly prepare if a borrow occurs in a subtract. Used in Digital VAX [C], Intel 80x86 [CF], Motorola 680x0 [C], Motorola 68300 [C], Motorola M68HC16 [C].
comparing indicator contains one of iii values: less, equal, or greater. Used in MIX.
extend Set to the value of the carry fleck for arithmetic operations (used to support implementation of multi-byte arithmetic larger than that implemented directly past the hardware. Used in Motorola 680x0 [Ten], Motorola 68300 [Ten].
half bear Set if a deport out of chip 3 of an operand occurs during BCD addition. Used in Motorola M68HC16 [H].
negative Fix if the nearly significant bit of a result is set up. Used in Digital VAX [N], Motorola 680x0 [N], Motorola 68300 [N], Motorola M68HC16 [N].
overflow Prepare if arithmetics overflow occurs. Used in Digital VAX [V], Intel 80x86 [OF], Motorola 680x0 [V], Motorola 68300 [V], Motorola M68HC16 [V].
overflow toggle a single flake that is either on or off. Used in MIX.
parity For odd parity machines, set to make an odd number of one $.25; for an even parity car, set to brand an even number of one bits. Used in Intel 80x86 [PF]. The IBM 360/370 has odd parity on retention.
sign Set for negative sign. Used in Intel 80x86 [SF].
trap Set for traps. Used in Intel 80x86 [TF].
zero Set if a result equals zero. Used in Digital VAX [Z], Intel 80x86 [ZF], Motorola 680x0 [Z], Motorola 68300 [Z], Motorola M68HC16 [Z].

Some atmospheric condition are determined by combining multiple flags. For example, if a processor has a negative flag and a aught flag, the equivalent of a positive flag is the case of both the negative and zero flags both simultaneously being cleared.

A few typical command flags (with processors that include them):

decimal overflow trap enable Set if decimal overflow occurs (or conversion error on a VAX). Used in Digital VAX [DV].
direction flag Determines the direction of string operations (gear up for autoincrement, cleared for autodecrement). Used in Intel 80x86 [DF].
floating underflow trap enable Set if floating underflow occurs. Used in Digital VAX [FU].
integer overflow trap enable Set if integer overflow occurs (or conversion fault on a VAX). Used in Digital VAX [IV].
interupt enable Set up if interrupts enabled. Used in Intel 80x86 [IF].
i/o privilege level Used to control access to I/O instructions and hardware (thereby seperating control over I/O from other supervisor/user states). Two $.25. Used in Intel 80x86 [IO PL].
nested task flag Used in Intel 80x86 [NF].
resume flag Used in Intel 80x86 [RF].
virtual 8086 mode Used to switch to virtual 8086 emulation. Used in Intel 80x86 [VM].

stack pointer

Stack pointers are used to implement a processor stack in retention. In many processors, accost registers can be used as generic data stack pointers and queue pointers. A specific stack pointer or accost register may be hardwired for certain instructions. The most common use is to shop return addresses, processor state information, and temporary variables for subroutines.

IBM 360/370: any of the 16 general purpose registers may be used every bit a stack pointer
Intel 8086/80286: defended stack pointer (SP) combined with stack segment pointer (SS) to create address of stack
Intel 80386: dedicated stack pointer (ESP) combined with stack segment arrow (SS) and the stack-frame base of operations pointer (EBP) to create accost of stack
Motorola 680x0, 68300: dedicated user stack pointer (USP, A7) and organization stack pointer (SSP, A7) for implicit stack pointer operations, too as assuasive any of the 8 address registers to be every bit explicit stack pointers

subroutine return pointer

Some RISC processors include a special subroutine return pointer rather than using a stack in memory. The return address for subroutine calls is stored in this register rather than in retentivity. More than one level of subroutine calls requires storing and saving the contents of this register to and from memory.

Motorola 88100: r1 is a 32 bit register containing the return pointer generated by bsr and jsr instructions; the register can be read or overwritten by software and can fifty-fifty be used every bit a temporary general purpose data annals

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Created: Feb xiv, 2001 (from asm.htm)

Last Updated: March 12, 2001

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