Is It Better To Use Storage Or Registers In Hdl

An assortment proclamation of a internet or variable tin can be either scalar or vector. Any number of dimensions can be created past specifying an accost range after the identifier proper name and is chosen a multi-dimensional assortment. Arrays are allowed in Verilog for reg, wire, integer and existent information types.

                      reg        y1 [eleven:0];        // y is an scalar reg array of depth=12, each 1-scrap wide 	wire [0:7] y2 [3:0]          // y is an viii-bit vector cyberspace with a depth of four 	reg  [7:0] y3 [0:one][0:3];    // y is a 2d array rows=ii,cols=4 each 8-bit broad

An index for every dimension has to be specified to admission a particular element of an array and tin can be an expression of other variables. An assortment tin can exist formed for whatever of the different data-types supported in Verilog.

Notation that a memory of n 1-bit reg is not the same equally an north-bit vector reg.

Consignment

                      y1 = 0; 						// Illegal - All elements can't be assigned in a unmarried become 	 	y2[0] = 8'ha2; 			// Assign 0xa2 to index=0  	y2[2] = 8'h1c; 			// Assign 0x1c to index=2 	y3[1][2] = 8'hdd; 	// Assign 0xdd to rows=1 cols=ii 	y3[0][0] = viii'haa; 	// Assign 0xaa to rows=0 cols=0

Example

The code shown below simply shows how dissimilar arrays can exist modeled, assigned and accessed. mem1 is an 8-bit vector, mem2 is an 8-bit array with a depth of 4 (specified by the range [0:iii]) and mem3 is a xvi-bit vector second array with 4 rows and 2 columns. These variables are assigned dissimilar values and printed.

                      module des ();   reg [7:0]  mem1; 							// reg vector 8-bit wide   reg [7:0]  mem2 [0:3]; 				// 8-scrap wide vector array with depth=4   reg [15:0] mem3 [0:3][0:one]; 	// 16-fleck wide vector 2d array with rows=four,cols=2      initial brainstorm     int i;          mem1 = 8'ha9;     $display ("mem1 = 0x%0h", mem1);          mem2[0] = 8'haa;     mem2[1] = 8'hbb;     mem2[2] = 8'hcc;     mem2[3] = viii'hdd;     for(i = 0; i < 4; i = i+1) begin       $display("mem2[%0d] = 0x%0h", i, mem2[i]);     end          for(int i = 0; i < 4; i += 1) begin       for(int j = 0; j < ii; j += 1) begin         mem3[i][j] = i + j;         $display("mem3[%0d][%0d] = 0x%0h", i, j, mem3[i][j]);       terminate     end   end endmodule

Simulation Log

ncsim> run mem1 = 0xa9 mem2[0] = 0xaa mem2[1] = 0xbb mem2[2] = 0xcc mem2[3] = 0xdd mem3[0][0] = 0x0 mem3[0][1] = 0x1 mem3[ane][0] = 0x1 mem3[1][1] = 0x2 mem3[2][0] = 0x2 mem3[2][1] = 0x3 mem3[3][0] = 0x3 mem3[three][ane] = 0x4 ncsim: *W,RNQUIE: Simulation is complete.

Memories

Memories are digital storage elements that help store a information and information in digital circuits. RAMs and ROMs are good examples of such memory elements. Storage elements can exist modeled using ane-dimensional arrays of blazon reg and is called a memory. Each element in the retentivity may represent a give-and-take and is referenced using a single array index.

memory array in verilog

Register Vector

Verilog vectors are alleged using a size range on the left side of the variable name and these get realized into flops that match the size of the variable. In the code shown below, the design module accepts clock, reset and some control signals to read and write into the cake.

It contains a 16-bit storage element chosen annals which simply gets updated during writes and returns the current value during reads. The register is written when sel and wr are high on the same clock edge. It returns the current information when sel is high and wr is low.

                      module des (    input           clk,                 input           rstn,                 input           wr,                 input           sel,                 input [15:0]    wdata,                 output [15:0]   rdata);  	reg [15:0] register;  	always @ (posedge clk) brainstorm     if (!rstn)     	annals <= 0;     else begin     	if (sel & wr)        	annals <= wdata;     	else       	register <= register;     end 	end  	assign rdata = (sel & ~wr) ? register : 0; endmodule

The hardware schematic shows that a 16-bit bomb is updated when control logic for writes are active and the current value is returned when control logic is configured for reads.

Assortment

In this example, register is an assortment that has four locations with each having a width of sixteen-bits. The design module accepts an additional input betoken which is called addr to access a particular index in the array.

                      module des (    input           clk,                 input           rstn,                 input  [1:0]    addr,                 input           wr,                 input           sel,                 input [15:0]    wdata,                 output [fifteen:0]   rdata);  reg [15:0] register [0:3]; integer i;  ever @ (posedge clk) begin     if (!rstn) begin         for (i = 0; i < 4; i = i+ane) begin              register[i] <= 0;         finish     cease else brainstorm         if (sel & wr)              register[addr] <= wdata;         else             annals[addr] <= register[addr];     end end   assign rdata = (sel & ~wr) ? register[addr] : 0; endmodule

Information technology can be seen in the hardware schematic that each index of the array is a 16-flake flop and the input address is used to access a detail set of flops.